1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and manufacturing method thereof, and more particularly to a semiconductor integrated circuit that has a clock distribution circuit and a manufacturing method thereof.
2. Description of the Related Art
Conventionally, in the development and manufacturing stages of an application specific integrated circuit (ASIC), clock skew is analyzed using a computer aided design (CAD) system, and clock skew is reduced based on the results of this analysis (see, for example, Unexamined Japanese Patent Publication No. HEI 9-269847). In clock skew analysis, a clock distribution circuit is used that has a buffer tree structure in which the system from the clock signal supply source to the flip-flops (buffers) in which clock signals are actually used is arranged in tree form.
FIG.4 shows the configuration of a typical clock distribution circuit used in clock skew analysis. The clock distribution circuit has a total of three circuit blocks 100, 200, and 300.
Circuit block 100 is the buffer tree that has the largest number of buffer stages (instances), and performs distribution to all areas of the semiconductor integrated circuit. A clock signal from the supply source is inputted to a mode switching selector 101, and this mode switching selector 101 distributes clock signal A1 in the case of mode 1, and clock signal B common to circuit blocks 100, 200, and 300 in the case of mode 2, to the buffer stages of the buffer tree.
Circuit block 200 is the buffer tree that has the next-largest number of buffer stages, and performs distribution to some areas of the semiconductor integrated circuit. A clock signal from the supply source is input to a mode switching selector 201, and this mode switching selector 201 distributes clock signal A2 in the case of mode 1, and common clock signal B in the case of mode 2, to the buffer stages of the buffer tree.
Circuit block 300 does not have any buffers in this example, but still performs distribution to some areas of the semiconductor integrated circuit. A clock signal from the supply source is input to a mode switching selector 301, and this mode switching selector 301 outputs clock signal A3 in the case of mode 1, and common clock signal B in the case of mode 2, directly to an output pin 302.
Here, in the case of mode 2, common clock signal B is supplied to circuit blocks 100, 200, and 300. In circuit block 100, there are many buffer stages, the depth of the buffer stages as far as which the clock signal from mode switching selector 101 is supplied is great, and the number of fanout branches of each buffer is large, and therefore the delay value up to a buffer (buffer stage) at which a clock signal from mode switching selector 101 is actually used is large.
On the other hand, in circuit block 200 there are few buffer stages, the depth of the buffer stages is shallow, and the number of fanout branches of each buffer is small, and therefore the delay value up to a buffer (buffer stage) at which a clock signal from mode switching selector 201 is actually used is small. In circuit block 300, there are no buffers, and therefore the delay value from mode switching selector 301 to output to external pin 302 is small.
Thus, in a clock distribution circuit, delay adjustment buffers are inserted in the clock signal supply paths from the supply source to the mode switching selectors, and clock skew regulation is performed by reducing the difference of the delay values of clock signals after leaving the mode switching selectors of the respective circuit blocks. To be specific, taking the largest delay value of circuit block 100 as a basis, delay adjustment buffers 210 through 212 are inserted between the supply source and mode switching selector 201, and delay adjustment buffers 310 through 314 are inserted between the supply source and mode switching selector 301.
In delay adjustment buffers 210 through 212 and 310 through 314, the number of fanout branches is “1” and the load capacity is small. On the other hand, in circuit block 100 that determines the number of delay adjustment buffer insertions, the the number of fanout branches of each buffer is large, and the load capacity is large. To obtain a delay value equal to that of circuit block 100, it is necessary to insert in circuit block 200 more delay adjustment buffers 210 through 212 than that number of buffers, and to insert in circuit block 300 more delay adjustment buffers 310 through 314 than that number of buffers. As a result, a difference arises in the final number of buffer stages of circuit block 200 from the supply source with respect to the final number of buffer stages of circuit block 100 from the supply source. Similarly, a difference also arises in the final number of buffer stages of circuit block 300 from the supply source.
When temperature variations or voltage variations occur, a difference in the number of buffer stages produces variation in clock skew. In general, in the case of high temperature and low voltage, the clock signal path wiring delay increases and the buffer transit delay (cell delay) decreases. On the other hand, in the case of low temperature and high voltage, the wiring delay decreases and the buffer transit delay increases. That is to say, even if delay adjustment buffers 210 through 212 and 310 through 314 are inserted and the delay values of circuit blocks 100, 200, and 300 are made uniform in an environment of normal temperature and normal voltage, clock skew due to differences in the number of buffer stages is generated by temperature variations and voltage variations.
In above-mentioned Patent Literature 1, a clock distribution circuit is proposed whereby the number of buffers and number of buffer stages are made uniform in all clock signal supply system circuit blocks, and even if temperature variations or voltage variations occur, clock skew does not occur between buffer stages of the same level of different circuit blocks.
However, an actual implementation method has not been established in a computer aided design system used in the development and manufacturing stages of a semiconductor integrated circuit. Actually, in order to make the number of buffers and number of buffer stages uniform, it is necessary to calculate the wiring delay of a part for which the delay value has been adjusted by delay adjustment buffer insertion, route wiring based on the result of this calculation, and perform delay value regulation appropriate to uniformity of the number of buffer stages.
Therefore, reducing clock skew without experiencing the effects of temperature variations or voltage variations involves great effort, such as wiring delay calculation and wiring routing, and at the same time there is a high degree of dependency in handling the task by routing wiring whose wiring delay is affected by temperature variations and voltage variations, making it impossible to reduce clock skew satisfactorily.